Corner effects in current shallow trench isolation regions (STI) architecture leads to undesirable high leakage current and gate oxide isolation (GOI) issues.
U.S. Pat. No. 5,539,229 to Nobel, Jr. et al. describes a semiconductor structure comprising a transistor having a gate conductor that has first and second edges bounded by raised isolation structures, e.g. STI. A source diffusion is self-aligned to the third edge and a drain diffusion is self-aligned to the fourth edge of the gate electrode.
U.S. Pat. No. 5,610,083 to Chan et al. describes a process for creating a back gate contact in an SOI layer that can be incorporated into a MOSFET fabrication recipe. The back gate consists of an etched trench lined with insulator and filled with doped polysilicon. The polysilicon filled trench electrically connects the semiconductor substrate to overlying metal contacts.
U.S. Pat. No. 5,525,533 to Woodruff et al. describes a low voltage coefficient MOS capacitor, and a method of making such a capacitor, having substantially uniform parasitic effects over an operating voltage range and a low voltage coefficient. The capacitor comprises a first conductive layer superjacent a silicon-on-insulator substrate. The first conductive layer comprises heavily doped silicon having a first conductivity type while the substrate comprises a second conductivity type. The conductor further comprises an isolation trench surrounding the first conductive layer filled with a dielectric material. Positioned superjacent the first conductive layer is a dielectric layer thereby forming a dielectric shell on all sides of the first conductive layer except for its upper face. A second conductive layer is positioned superjacent the dielectric layer to form a low voltage coefficient capacitor.
U.S. Pat. No. 5,892,707 to Noble describes a memory array including a semiconductor substrate, an isolation trench disposed in the substrate, and a conductor that is disposed in the trench. The array also includes a memory cell that is coupled to the conductor in the trench. The conductor may be a digit line that is coupled to a source/drain of the memory cell or to a shared source/drain region of a pair of adjacent memory cells.